SI53115 Datasheet, PDF (28/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
Pin #
54
55
56
57
58
59
60
61
62
63
64
Table 25. Si53115 64-Pin QFN Descriptions (Continued)
Name
DIF_11
DIF_12
DIF_12
GND
VDD
DIF_13
DIF_13
DIF_14
DIF_14
VDD_IO
GND
Type
Description
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
GND Ground for outputs.
3.3 V 3.3 V power supply for outputs.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
VDD Power supply for differential outputs.
GND Ground for outputs.
28
Rev. 1.1