SI53115 Datasheet, PDF (25/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

5. Pin Descriptions: 64-Pin QFN
VDDA 1
GNDA 2
100M_133M 3
HBW_BYPASS_LBW 4
PWRGD / PWRDN 5
GND 6
VDDR 7
CLK_IN 8
CLK_IN 9
SA_0 10
SDA 11
SCL 12
SA_1 13
FBOUT_NC 14
FBOUT_NC 15
GND 16
Si53115
Si53115
48 ^VDD_IO
47 ^GND
46 ^DIF_9
45 ^DIF_9
44 ^DIF_8
43 ^DIF_8
42 GND
41 ^VDD
40 DIF_7
39 DIF_7
38 DIF_6
37 DIF_6
36 VDD_IO
35 GND
34 _{DIF_5}
33 _{DIF_5}
Rev. 1.1
25