English
Language : 

SI53115 Datasheet, PDF (1/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER
Si53115
15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER
Features
 Fifteen 0.7 V low-power, push-  Separate VDDIO for outputs
pull HCSL PCIe Gen3 outputs  PLL or bypass mode
 100 MHz /133 MHz PLL
 Spread spectrum tolerable

operation, supports PCIe and
QPI

PLL bandwidth SW SMBUS
programming overrides the latch


1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
value from HW pin
 Low phase jitter (Intel QPI, PCIe
 9 selectable SMBUS addresses
Gen 1/2/3/4 common clock
compliant)

SMBus address configurable to
allow multiple buffers in a single

Gen 3 SRNS Compliant
control network 3.3 V supply  100 ps input-to-output delay
voltage operation
 Extended Temperature:
–40 to 85 °C
 64-pin QFN
Ordering Information:
See page 30.
Pin Assignments
Applications
 Server
 Storage
 Data center
 Enterprise switches and routers
Description
The Si53115 is a 15-output, low-power HCSL differential clock buffer that
meets all of the performance requirements of the Intel DB1200ZL
specification. The device is optimized for distributing reference clocks for
Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/
Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output can be enabled through I2C
for maximum flexibility and power savings. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it
for free at www.silabs.com/pcie-learningcenter.
VDDA 1
GNDA 2
100M_133M 3
HBW_BYPASS_LBW 4
PWRGD / PWRDN 5
GND 6
VDDR 7
CLK_IN 8
CLK_IN 9
SA_0 10
SDA 11
SCL 12
SA_1 13
FBOUT_NC 14
FBOUT_NC 15
GND 16
Si53115
Patents pending
48 VDD_IO
47 GND
46 DIF_9
45 DIF_9
44 DIF_8
43 DIF_8
42 GND
41 VDD
40 DIF_7
39 DIF_7
38 DIF_6
37 DIF_6
36 VDD_IO
35 GND
34 DIF_5
33 DIF_5
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53115