SI53115 Datasheet, PDF (15/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
2.4.1. PWRDN Assertion
When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held LOW/
LOW on the next DIF high-to-low transition.
PWRDWN
DIF
DIF
Figure 1. PWRDN Assertion
2.4.2. CKPWRGD Assertion
The power up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion
of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs
stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN
deassertion to a voltage greater than 200 mV.
Tstable
<1.8 ms
DIF
DIF
Tdrive_Pwrdn#
<300 µs; > 200 mV
Figure 2. PWRDG Assertion (Pwrdown—Deassertion)
Rev. 1.1
15