SI53115 Datasheet, PDF (21/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
4.3. Control Registers
Table 17. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register
Bit
Description
If Bit = 0 If Bit = 1 Type
Default
Output(s)
Affected
0
100M_133M#
133 MHz 100 MHz
R
Latched at DIF[11:0]
Frequency Select
power up
1
Reserved
0
2
Reserved
0
3 Output Enable DIF 13 Low/Low
Enable
RW
1
DIF_13
4 Output Enable DIF 14 Low/Low
Enable
RW
1
DIF_14
5
Reserved
0
6
PLL Mode 0
See PLL Operating Mode
R
Latched at
Readback Table
power up
7
PLL Mode 1
See PLL Operating Mode
R
Latched at
Readback Table
power up
Table 18. Byte 1: Output Enable Control Register
Bit
Description
If Bit = 0 If Bit = 1
Type
Default Output(s)
Affected
0
Reserved
0
1
Output Enable DIF 0
Low/Low
Enabled
RW
1
DIF[0]
2
Output Enable DIF 1
Low/Low
Enabled
RW
1
DIF[1]
3
Output Enable DIF 2
Low/Low
Enabled
RW
1
DIF[2]
4
Output Enable DIF 3
Low/Low
Enabled
RW
1
DIF[3]
5
Output Enable DIF 4
Low/Low
Enabled
RW
1
DIF[4]
6
Reserved
0
7
Output Enable DIF 5
Low/Low
Enabled
RW
1
DIF[5]
Rev. 1.1
21