SI53115 Datasheet, PDF (10/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)¹
Parameter
Symbol
CLK 100 MHz, 133 MHz
Unit
Clock Stabilization Time²
Long Term Accuracy^3,4,5
Absolute Host CLK Period (100 MHz)^3,4,6
Absolute Host CLK Period (133 MHz)^3,4,6
Slew Rate^3,4,7
Rise Time Variation^3,8,9
Fall Time Variation^3,8,9
Rise/Fall Matching^3,8,10,11
Voltage High (typ 0.7 V)^3,8,12
Voltage Low (typ 0.7 V)^3,8,13
Maximum Voltage
Minimum Voltage
Absolute Crossing Point Voltages^3,8,14,15,16
Total Variation of Vcross Over All Edges ^3,8,18
Duty Cycle^3,5
Maximum Voltage (Overshoot) ^3,8,19
T_STAB
L_ACC
T_ABS
T_ABS
Edge_rate
∆ Trise
∆ Tfall
T_{RISE_MAT}/T_{FALL_MAT}
V_HIGH
V_LOW
V_MAX
V_MIN
Vox_ABS
Total ∆ Vox
DC
V_ovs
Min
—
—
9.94900
7.44925
1.0
—
—
—
660
–150
—
–300
300
—
45
—
Typ
Max
1.5
1.8
ms
—
100
ppm
—
10.05100 ns
—
7.55075 ns
3.0
4.0
V/ns
—
125
ps
—
125
ps
7
20
%
750
850
mV
15
150
mV
850
1150
mV
—
—
mV
450
550
mV
14
140
mV
—
55
%
—
V_High + 0.3 V
10
Rev. 1.1