SI53115 Datasheet, PDF (12/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
Table 8. Clock Periods Differential Clock Outputs with SSC Disabled
SSC OFF
Center
Freq, MHz
1 Clock
1 µs
Measurement Window
0.1 s
0.1 s
0.1 s
Unit
1 µs
1 Clock
–C-C
Jitter
AbsPer
Min
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
+C-C
Jitter
AbsPer
Max
100.00 9.94900
9.99900 10.00000 10.00100
10.05100
ns
133.33 7.44925
7.49925 7.50000 7.50075
7.55075
ns
Table 9. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Center
Freq, MHz
1 Clock
1 µs
Measurement Window
0.1 s
0.1 s
0.1 s
Unit
1 µs
1 Clock
–C-C
Jitter
AbsPer
Min
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
+C-C
Jitter
AbsPer
Max
99.75
9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126
ns
133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845
ns
Table 10. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
3.3 V Core Supply Voltage¹
VDD/VDD_A
—
4.6
3.3 V I/O Supply Voltage¹
VDD_IO
—
4.6
3.3 V Input High Voltage^1,2
VIH
—
4.6
3.3 V Input Low Voltage¹
VIL
−0.5
—
Storage Temperature¹
Input ESD protection³
t_s
–65
150
ESD
2000
—
Notes:
1. Consult manufacturer regarding extended operation in excess of normal DC operating parameters.
2. Maximum VIH is not to exceed maximum V_DD.
3. Human body model.
Unit
V
V
V
V
°C
V
12
Rev. 1.1