SI53115 Datasheet, PDF (5/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
Table 2. SMBus Characteristics
Parameter
SMBus Input Low Voltage¹
SMBus Input High Voltage¹
SMBus Output Low Voltage¹
Nominal Bus Voltage¹
SMBus Sink Current¹
SCLK/SDAT Rise Time¹
SCLK/SDAT Fall Time¹
SMBus Operating Frequency^{1, 2}
Symbol
V_ILSMB
V_IHSMB
V_OLSMB
V_DDSMB
I_PULLUP
t_RSMB
t_FSMB
f_MINSMB
Test Condition
@ I_PULLUP
@ V_OL
3 V to 5 V +/-10%
(Max V_IL – 0.15) to (Min V_IH + 0.15)
(Min V_IH + 0.15) to (Max V_IL – 0.15)
Minimum Operating Frequency
Notes:
1. Guaranteed by design and characterization.
2. The differential input clock must be running for the SMBus to be active.
Min Max Unit
0.8
V
2.1 V_DDSMB V
0.4
V
2.7
5.5
V
4
mA
1000
ns
300
ns
100
kHz
Table 3. Current Consumption
T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min Typ Max Unit
Operating Current
IDD_VDD
133 MHz, VDD Rail
—
IDD_VDDA 133 MHz, VDDA + VDDR, PLL Mode —
IDD_VDDIO 133 MHz, CL = Full Load, VDD IO Rail —
Power Down Current IDD_VDDPD
Power Down, VDD Rail
—
IDD_VDDAPD
Power Down, VDDA Rail
—
IDD_VDDIOPD
Power Down, VDD_IO Rail
—
25
30
mA
20
25
mA
100 110 mA
0.5
1
mA
4
7
mA
0.4
0.7
mA
Rev. 1.1
5