SI53115 Datasheet, PDF(2/33 Page) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

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SI53115 Datasheet, PDF (2/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

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Si53115

Functional Block Diagram

CLK_IN

100M_133

HBW_BYPASS_LBW

SA_0

SA_1

PWRGD / PWRDN

SDA

SCL

SSC Compatible

PLL

Control

Logic

FB_OUT

DIF_[14:0]

Rev. 1.1

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