SI53115 Datasheet, PDF (18/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
Skew measurement
point
0.000 V
High Duty Cycle %
TPeriod
Low Duty Cycle %
Figure 5. Differential (CLOCK–CLOCK) Measurement Points (T_period, Duty Cycle, Jitter)
3.2. Termination of Differential Outputs
All differential outputs are to be tested into a 100  or 85  differential impedance transmission line. Source
terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be
supported. For CPU outputs, a maximum trace length of 10” and a maximum of 200 MHz are assumed. For SRC
clocks, a maximum trace length of 16” and maximum frequency of 100 MHz is assumed. For frequencies beyond
200 MHz, trace lengths must be restricted to avoid signal integrity problems.
Table 16. Differential Output Termination
Clock
Board Trace Impedance Rs
Rp Unit
DIFF Clocks—50  configuration
100
33+5% N/A 
DIFF Clocks—43  configuration
85
27+5% N/A 
3.2.1. Termination of Differential NMOS Push-Pull Type Outputs
Clock ^Rs
T-Line
10" Typical
Receiver
2 pF
Source Terminated
2 pF
Clock # ^Rs
T-Line
10" Typical
Figure 6. 0.7 V Configuration Test Load Board Termination for NMOS Push-Pull
18
Rev. 1.1