SI53115 Datasheet, PDF (13/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
2. Functional Description
2.1. CLK_IN, CLK_IN
The differential input clock is expected to be sourced from a clock synthesizer or PCH.
2.2. 100M_133M—Frequency Selection
The Si53115 is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.
100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.
Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53115 is operated in 1:1
mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-down
resistor is attached to this pin to select the input/output frequency. The functionality is summarized in Table 11.
Table 11. Frequency Program Table
100M_133M
0
1
Optimized Frequency (DIF_IN = DIF_x)
133.33 MHz
100.00 MHz
Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner.
2.3. SA_0, SA_1—Address Selection
SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53115. These are the
two tri-level input pins that can configure the device to nine different addresses.
Table 12. SMBUS Address Table
SA_1
L
L
L
M
M
M
H
H
H
SA_0
L
M
H
L
M
H
L
M
H
SMBUS Address
D8
DA
DE
C2
C4
C6
CA
CC
CE
Rev. 1.1
13