SI53115 Datasheet, PDF (26/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
Table 25. Si53115 64-Pin QFN Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
Type
Description
VDDA
3.3 V 3.3 V power supply for PLL.
GNDA
GND Ground for PLL.
100M_133M
HBW_BYPASS_LBW
PWRGD/PWRDN
I,SE 3.3 V tolerant inputs for input/output frequency selection. An external pull-
up or pull-down resistor is attached to this pin to select the input/output
frequency.
High = 100 MHz output
Low = 133 MHz output
I, SE
Tri-Level input for selecting the PLL bandwidth or bypass mode.
High = High BW mode
Med = Bypass mode
Low = Low BW mode
I 3.3 V LVTTL input to power up or power down the device.
GND
GND Ground for outputs.
VDDR
CLK_IN
VDD 3.3 V power supply for differential input receiver. This VDDR should be
treated as an analog power rail and filtered appropriately.
I, DIF 0.7 V Differential input.
CLK_IN
I, DIF 0.7 V Differential input.
SA_0
I,PU 3.3 V LVTTL input selecting the address. Tri-level input.
SDA
I/O Open collector SMBus data.
SCL
I/O SMBus slave clock input.
SA_1
I,PU 3.3 V LVTTL input selecting the address. Tri-level input.
FBOUT_NC
FBOUT_NC
GND
I/O Complementary differential feedback output. There are active signals on
Pins 15 and 16, do not connect anything to this pin.
I/O True differential feedback output. There are active signals on Pins 15 and
16; do not connect anything to Pin 15.
GND Ground for outputs.
DIF_0
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_0
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
VDDIO
3.3 V 3.3 V power supply for differential outputs.
GND
GND Ground for outputs.
DIF_1
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_1
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_2
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_2
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
26
Rev. 1.1