SI53115 Datasheet, PDF (31/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
8. Package Outline
Figure 12 illustrates the package details for the Si53115. Table 26 lists the values for the dimensions shown in the
illustration.
Figure 12. 64-Pin Quad Flat No Lead (QFN) Package
Table 26. Package Dimensions^1,2,3,4
Dimension
Min
Nom
Max
Dimension
Min
A
0.80
0.85
0.90
E2
3.90
A1
0.00
0.02
0.05
L
0.30
b
0.15
0.20
0.25
aaa
—
D
6.00 BSC.
bbb
—
D2
3.90
4.00
4.10
ccc
—
e
0.40 BSC.
ddd
—
E
6.00 BSC.
Nom
Max
4.00
4.10
0.40
0.50
—
0.10
—
0.10
—
0.08
—
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.1
31