SI5375 Datasheet, PDF (47/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5375
Table 9. Si5375 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal
Level
Description
G5
SCL
I LVCMOS _I²_{C Serial Clock.}
This pin functions as the serial clock input.
This pin has a weak pull-down.
G6
SDA
I/O LVCMOS _I²_{C Serial Data.}
I²C pin functions as the bi-directional serial data port.
B1
CKOUT1P_A ^O
Multi _{Output Clock for DSPLLq.}
A2
CKOUT1N_A
A9
CKOUT1P_B
B9
CKOUT1N_B
J9
CKOUT1P_C
J8
CKOUT1N_C
Differential output clock with a frequency range of 0.002 to
808 MHz. Output signal format is selected by SFOUT_REG
register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive in
phase single-ended clock outputs at the same frequency.
J1
CKOUT1P_D
H1
A4, A5
CKOUT1N_D
NC
N/A
N/A _{No Connection.}
C3, C6
C7, D3
D9, E1
Leave floating. Make no external connections to this pin for
normal operation.
E9, F1
F7, G3
G4, G7
J5, J6
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5375 Register Map.
Rev. 1.0
47