SI5375 Datasheet, PDF (46/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5375
Table 9. Si5375 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal
Level
Description
B2
GND
GND Supply Ground for each DSPLLq.
A3
GND
B3
GND
E4
GND
C8
GND
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. See
recommended layout.
A8
GND
B8
GND
C9
GND
H7
GND
J7
GND
H8
GND
H9
GND
G1
GND
H2
GND
J2
GND
G2
GND
C2
CKIN1P_A
I
Multi _{Clock Input for DSPLLq.}
D2
CKIN1N_A
B7
CKIN1P_B
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency range is 2 kHz to 710 MHz.
B6
CKIN1N_B
G8
CKIN1P_C
F8
CKIN1N_C
H3
CKIN1P_D
H4
CKIN1N_D
E2
LOL_A
O LVCMOS DSPLLq Loss of Lock Indicator.
C5
LOL_B
These pins function as the active high PLL loss of lock indicator
E8
LOL_C
if the LOL_PIN register bit is set to 1.
H5
LOL_D
0 = PLL locked.
1 = PLL unlocked.
If LOL_PINn = 0, this pin will tri-state. Active polarity is
controlled by the LOL_POLn bit. The PLL lock status will always
be reflected in the LOL_INT read only register bit.
D1
CS_CA_A
I LVCMOS _{DSPLLq Input Clock Select/Active Clock Indicator.}
A6
CS_CA_B
F9
CS_CA_C
J4
CS_CA_D
Input: This pin functions as the input clock selector between
CKIN and OSC.
0 = Select CKIN1.
1 = Select OSC (Internal).
Must be high or low. Do not float. If a DSPLL is not used, its
CS_CA_q pin should be tied high.
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5375 Register Map.
46
Rev. 1.0