SI5375 Datasheet, PDF(26/54 Page) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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SI5375 Datasheet, PDF (26/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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Si5375

Bit

Name

CLAT [7:0]

Type

R/W

Reset value = 0000 0000

Bit

Name

Function

7:0 CLAT [7:0] CLAT [7:0].

With INCDEC_PIN = 0, this register sets the phase delay for CKOUT in units of 1/Fosc.

This can take as long as 20 seconds.

01111111 = 127/Fosc (2s compliment)

00000000 = 0

10000000 = â128/Fosc (2s compliment)

Bit

Name FLAT_VALID

FLAT [14:8]

Type

R/W

Reset value = 1000 0000

Bit

Name

Function

7 FLAT_VALID FLAT_VALID.

Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the

existing FLAT[14:0] value to be held internally for use while the new value is being

written. Once the new FLAT[14:0] value is completely written, set FLAT_VALID = 1 to

enable its use.

0: Memorize existing FLAT[14:0] value and ignore intermediate register values during

write of new FLAT[14:0] value.

1: Use FLAT[14:0] value directly from registers.

6:0 FLAT [14:8] FLAT [14:8].

Fine resolution control for overall device latency from input clocks to output clocks.

Positive values increase the skew. See DSPLLsim for details.

Rev. 1.0

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