SI5375 Datasheet, PDF (21/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

7. Register Descriptions
Si5375
Register 0.
Bit
D7
D6
D5
D4 D3 D2
D1
D0
Name
FREE_RUN CKOUT_ALWAYS_ON
BYPASS_REG
Type
R
R/W
R/W
R
R
R
R/W
R
Reset value = 0001 0100
Bit
Name
Function
7
Reserved
6
FREE_RUN
Free Run.
This bit configures free run operation. The OSC_P/N in internally routed to the
DSPLL. This allows the device to lock to its OSC reference.
0: Disable
1: Enable
5 CKOUT_ALWAYS_ON CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL
is on and ICAL is not complete or successful.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output.
Notes:
1. The frequency may be significantly off until the part is calibrated.
2. Must be 1 to control output to output skew.
4:2
Reserved
1
BYPASS_REG Bypass Register.
This bit enables or disables the PLL bypass mode. Use only when the device is
in digital hold or before the first ICAL. BYPASS mode is not supported with
CMOS clock outputs.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypass-
ing PLL.
0
Reserved
Rev. 1.0
21