SI5375 Datasheet, PDF (27/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5375
Register 18.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
FLAT [7:0]
Type
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0 FLAT [7:0] FLAT [7:0].
Fine resolution control for overall device latency from input clocks to output clocks.
Positive values increase the skew. See DSPLLsim for details.
Register 19.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
VALTIME [1:0]
LOCKT [2:0]
Type
R
R
R
R/W
R/W
Reset value = 0010 1100
Bit
Name
Function
7:5
Reserved
4:3 VALTIME [1:0] VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 seconds
2:0 LOCKT [2:0] LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is
triggered by phase slip in DSPLL.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: .833 ms
Rev. 1.0
27