SI5375 Datasheet, PDF (23/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5375
Register 3.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
VCO_FREEZE SQ_ICAL
Type
R
R
R/W
R/W
R
R
R
R
Reset value = 0000 0101
Bit
Name
Function
7:6
Reserved
5 VCO_FREEZE VCO_FREEZE.
Forces the part into VCO Freeze. This bit overrides all other manual and automatic
clock selection controls.
0: Normal operation.
1: Force VCO Freeze mode. Overrides all other settings and ignores the quality of all of
the input clocks.
4
SQ_ICAL SQ_ICAL.
This bit determines if the output clock will remain enabled or be squelched (disabled)
during an internal calibration.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0
Reserved
Register 5.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
ICMOS [1:0]
Type
R/W
R
R
R
R
R
R
Reset value = 1110 1101
Bit
Name
Function
7:6 ICMOS [1:0] ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buffer drive
strength. These values assume CKOUT+ is tied to CKOUT–.
00: 8 mA
01: 16 mA
10: 24 mA
11: 32 mA
5:0 Reserved
Rev. 1.0
23