SI5375 Datasheet, PDF (15/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

4. Functional Description
Si5375
CKIN1P_A
CKIN1N_A
Input Stage PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Synthesis Stage
DSPLL^®
A
fOSC
÷ NC1_HS
Output Stage
PLL Bypass
÷ NC1
CKOUT1P_A
CKOUT1N_A
CKIN1P_B
CKIN1N_B
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
÷ N2
DSPLL^®
B
fOSC
÷ NC1_HS
PLL Bypass
÷ NC1
CKOUT1P_B
CKOUT1N_B
CKIN1P_C
CKIN1N_C
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
÷ N2
DSPLL^®
C
fOSC
÷ NC1_HS
PLL Bypass
÷ NC1
CKOUT1P_C
CKOUT1N_C
CKIN1P_D
CKIN1N_D
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
÷ N2
DSPLL^®
D
fOSC
÷ NC1_HS
PLL Bypass
÷ NC1
CKOUT1P_D
CKOUT1N_D
÷ N2
RSTL_q
CS_q
Status / Control
High PSRR
Voltage Regulator
VDD_q
GND
SCL SDA LOL_q IRQ_q
OSC_P/N
Low Jitter
XO or Clock
Figure 5. Functional Block Diagram
The Si5375 is a highly integrated jitter-attenuating clock multiplier that integrates four fully independent DSPLLs
and provides ultra-low jitter generation with less than 410 fs RMS. The device accepts clock inputs ranging from
2 kHz to 710 MHz and generates independent, synchronous clock outputs ranging from 2 kHz to 808 MHz for each
DSPLL. Virtually any frequency translation (M/N) combination across its operating range is supported. The Si5375
supports a digitally programmable loop bandwidth that can range from 60 Hz to 8.4 kHz requiring no external loop
filter components. An external single-ended or differential reference clock or XO is required for the device to enable
ultra-low jitter generation and jitter attenuation. The Si5375 uses this external reference clock as both a jitter and
holdover reference. The reference clock can be either single-ended or differential and should be connected to the
OSC_P pin (and the OSC_N pin for differential signaling). Because there is very little jitter attenuation from the
OSC_P and OSC_N pins to the output clocks, a low-jitter reference clock is strongly recommended. The stability
during holdover is determined by the stability of the reference clock. For more details, see the description of
RATE_REG (register 2 on page 12) and the Any-Frequency Precision Clocks Family Reference Manual, which can
be downloaded from http://www.silabs.com/timing. The reference oscillator can be internally routed into CKIN2_q,
so free-running clock generation is supported for each DSPLL offering simultaneous synchronous and
asynchronous operation. Configuration and control of the Si5375 is primarily handled through the I²C interface.
The device monitors each input clock for Loss-of-Signal (LOS) and provides a LOS alarm when missing pulses on
any of the input clocks are detected. The device monitors the lock status of each DSPLL and provides a Loss-of-
Lock (LOL) alarm when the DSPLL is unlocked. The lock detect algorithm continuously monitors the phase of the
selected input clock in relation to the phase of the feedback clock. The Si5375 provides a VCO freeze capability
that allows the device to continue generation of a stable output clock when the input reference is lost.
The output drivers are configurable to support common signal formats, such as LVPECL, LVDS, CML, and CMOS
loads. If the CMOS signal format is selected, each differential output buffer generates two in-phase CMOS clocks
at the same frequency. For system-level debugging, a bypass mode drives the clock output directly from the
selected input clock, bypassing the internal DSPLL.
Silicon Laboratories offers a PC-based software utility, Si537xDSPLLsim that can be used to determine valid
frequency plans and loop bandwidth settings to simplify device setup. Si537xDSPLLsim provides the optimum
input, output, and feedback divider values for a given input frequency and clock multiplication ratio that minimizes
phase noise. This utility can be downloaded from http://www.silabs.com/timing. For further assistance, refer to the
Si53xx Any-Frequency Precision Clocks Family Reference Manual.
Rev. 1.0
15