SI5375 Datasheet, PDF (11/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5375
Table 5. Performance Specifications
V_DD = 1.8 V ±5% or 2.5 V ±10%, T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
PLL Performance*
Lock Time
Output Clock Phase Change
t_LOCKMP
t_{P_STEP}
Start of ICAL to of LOL
After clock switch
f3  128 kHz
—
35
—
200
Closed Loop Jitter Peaking
Jitter Tolerance
J_PK
J_TOL
—
0.05
Jitter Frequency Loop Band-
width
5000/BW
—
1 kHz Offset
—
–106
Phase Noise
fout = 622.08 MHz
CKO_PN
10 kHz Offset
100 kHz Offset
—
–114
—
–116
1 MHz Offset
—
–132
Subharmonic Noise
SP_SUBH
Phase Noise
@ 100 kHz Offset
—
–88
Spurious Noise
SP_SPUR
Max spur @ n x F3
(n  1, n x F3 < 100 MHz)
—
–70
Jitter Generation
J_GEN
f_IN = f_OUT = 622.08 MHz,
BW = 120 Hz
LVPECL output
12 kHz–20 MHz
—
350
50 kHz–80 MHz
—
410
*Note: fin = fout = 622.08 MHz; BW = 120 Hz; LVDS.
Max Unit
1200 ms
—
ps
0.1
dB
—
ns
pk-pk
— dBc/Hz
— dBc/Hz
— dBc/Hz
— dBc/Hz
—
dBc
—
dBc
410 fs rms
— fs rms
Rev. 1.0
11