SI5375 Datasheet, PDF (2/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5375
Functional Block Diagram
CKIN1P_A
CKIN1N_A
CKIN1P_B
CKIN1N_B
CKIN1P_C
CKIN1N_C
CKIN1P_D
CKIN1N_D
RSTL_q
CS_q
Input Stage PLL Bypass
÷ N31
Input
Monitor
f₃
÷ N32
PLL Bypass
÷ N31
Input
Monitor
f₃
÷ N32
PLL Bypass
÷ N31
Input
Monitor
f₃
÷ N32
PLL Bypass
÷ N31
Input
Monitor
f₃
÷ N32
Synthesis Stage
DSPLL^®
A
f_OSC
÷ NC1_HS
÷ N2
DSPLL^®
B
f_OSC
÷ NC1_HS
÷ N2
DSPLL^®
C
f_OSC
÷ NC1_HS
÷ N2
DSPLL^®
D
f_OSC
÷ NC1_HS
÷ N2
Status / Control
SCL SDA LOL_q IRQ_q
OSC_P/N
Low Jitter
XO or Clock
Output Stage
PLL Bypass
÷ NC1
PLL Bypass
÷ NC1
PLL Bypass
÷ NC1
PLL Bypass
÷ NC1
High PSRR
Voltage Regulator
CKOUT1P_A
CKOUT1N_A
CKOUT1P_B
CKOUT1N_B
CKOUT1P_C
CKOUT1N_C
CKOUT1P_D
CKOUT1N_D
VDD_q
GND
2
Rev. 1.0