SI5375 Datasheet, PDF (22/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5375
Register 2.
Bit
D7
D6
D5
D4
Name
BWSEL_REG [3:0]
Type
R/W
D3
D2
D1
D0
RATE_REG [3:0]
R/W
Reset value = 0100 0010
Bit
Name
Function
7:4 BWSEL_REG [3:0] BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the Si537xDSPLLsim software for
settings. After BWSEL_REG is written with a new value, an ICAL is required for
the change to take effect.
3:0
RATE_REG [3:0] RATE Setting for Oscillator.
Set these for the frequency of the oscillator connected to OSC_P/OSC_N pins.
An external oscillator or other clock source must be used. It is not possible to
use just a crystal.
Setting
0101
0110
All others
reserved
Minimum
37 MHz
109 MHz
Recommended
40 MHz
114.285 MHz
Maximum
41 MHz
125.5 MHz
22
Rev. 1.0