SI5375 Datasheet, PDF(45/54 Page) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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SI5375 Datasheet, PDF (45/54 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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Si5375

Pin #

Pin Name

RSTL_A

RSTL_B

RSTL_C

RSTL_D

IRQ_A

IRQ_B

IRQ_C

IRQ_D

Table 9. Si5375 Pin Descriptions

I/O Signal

Level

Description

I LVCMOS External Reset.

Active low input that performs external hardware reset of all four

DSPLLs. Resets all internal logic to a known state and forces

the device registers to their default value. Clock outputs are tri-

stated during reset. The part must be programmed after a reset

or power-on to get a clock output. This pin has a weak pull-up.

O LVCMOS DSPLLq Interrupt Indicator.

This pin functions as a device interrupt output. The interrupt

output, IRQ_PINn must be set to 1. The pin functions as a

maskable interrupt output with active polarity controlled by the

IRQ_POLn register bit.

0 = CKINn present

1 = LOS on CKINn

The active polarity is controlled by CK_BAD_POL. If no function

is selected, the pin tri-states.

C1, C4, B5

A7, D5, D7

E7, F5, G9

E3, F3, J3

VDD_A

VDD_B

VDD_C

VDD_D

VDD Supply Supply.

The device operates from a 1.8 or 2.5 V supply. A 0.1 ÂµF bypass

capacitive is required for every VDD_q pin. Bypass capacitors

should be associated with the following VDD_q pins:

0.1 ÂµF per VDD pin.

Four 1.0 ÂµF should also be placed as close to each VDD domain

as is practical. See recommended layout.

OSC_P

I Analog External OSC.

OSC_N

An external low jitter reference clock should be connected to

these pins. See the any-frequency precision clocks family

reference manual for oscillator selection details.

Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5375 Register Map.

Rev. 1.0

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