SI4464 Datasheet, PDF (39/56 Pages) Silicon Laboratories – HIGH-PERFORMANCE

Si4464/63/61/60
6. Data Handling and Packet Handler
6.1. RX and TX FIFOs
Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 16. Writing to
command Register 66h loads data into the TX FIFO, and reading from command Register 77h reads data from the
RX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the “TX_FIFO_EMPTY”
property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty threshold. If more data
is not loaded into the FIFO, the chip automatically exits the TX state after the PACKET_SENT interrupt occurs. The
RX FIFO has one programmable threshold, which is programmed by setting the “RX_FIFO_FULL” property. When
the incoming RX data crosses the Almost Full Threshold, an interrupt will be generated to the microcontroller via
the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. The RX Almost Full Threshold
indication implies that the host can read at least the threshold number of bytes from the RX FIFO at that time. Both
the TX and RX FIFOs may be cleared or reset with the “FIFO_RESET” command.
TX FIFO
RX FIFO
RX FIFO Almost
Full Threshold
TX FIFO Almost
Empty Threshold
Figure 16. TX and RX FIFOs
6.2. Packet Handler
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. The usual
fields for network communication, such as preamble, synchronization word, headers, packet length, and CRC, can
be configured to be automatically added to the data payload. The fields needed for packet generation normally
change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload
in TX mode and automatically checking them in RX mode greatly reduces the amount of communication between
the microcontroller and Si446x. It also greatly reduces the required computational power of the microcontroller. The
general packet structure is shown in Figure 17. Any or all of the fields can be enabled and checked by the internal
packet handler.
Pre a mb le
1-255 Bytes
1-4 Bytes
Con fig
0, 2, or 4
Byt es
Conf ig
0, 2, or 4
Byt es
Con fig
0, 2, o r 4
B ytes
Con fig
Figure 17. Packet Handler Structure
Con fig
0, 2, or 4
Bytes
0, 2, or 4
Bytes
Rev 1.2
39