SI4464 Datasheet, PDF (35/56 Pages) Silicon Laboratories – HIGH-PERFORMANCE

Si4464/63/61/60
9.0
4.1
10.0
4.5
11.0
5.0
12.0
6.0
13.0
8.0
14.0
10.0
15.0
20.0
The ramping profile is close to a linear ramping profile with smoothed out corner when approaching Vhi and Vlo.
The TXRAMP pin can source up to 1 mA without voltage drooping. The TXRAMP pin’s sinking capability is
equivalent to a 10 k pull-down resistor.
Vhi = 3 V when Vdd > 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be
smaller also.
Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10uA need to be sunk into the chip, Vlo will be
10 µA x 10k = 100 mV.
Number
0x2200
0x2201
0x2202
0x2203
Command
PA_MODE
PA_PWR_LVL
PA_BIAS_CLKDUTY
PA_TC
Summary
Sets PA type.
Adjust TX power in fine steps.
Adjust TX power in coarse steps
and optimizes for different
match configurations.
Changes the ramp up/down time
of the PA.
5.4.1. Si4464/63: +20 dBm PA
The +20 dBm configuration utilizes a class-E matching configuration. Typical performance for the 900 MHz band
for output power steps, voltage, and temperature are shown in Figures 10–12. The output power is changed in 128
steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer
to the PA Matching application note.
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
0
TX Power vs. PA_PWR_LVL
10 20 30 40 50 60 70 80 90 100 110 120
PA_PWR_LVL
Figure 10. +20 dBm TX Power vs. PA_PWR_LVL
Rev 1.2
35