SI4464 Datasheet, PDF (32/56 Pages) Silicon Laboratories – HIGH-PERFORMANCE

Si4464/63/61/60
The RSSI values and curves may be offset by the MODEM_RSSI_COMP API property. The default value of 7’h32
corresponds to no RSSI offset. Setting a value less than 7’h32 corresponds to a negative offset, and a value higher
than 7’h32 corresponds to a positive offset. The offset value is in 1 dB steps. For example, setting a value of 7’h3A
corresponds to a positive offset of 8 dB.
Clear channel assessment (CCA) or RSSI threshold detection is also available. An RSSI threshold may be set in
the MODEM_RSSI_THRESH API property. If the RSSI value is above this threshold, an interrupt or GPIO may
notify the host. Both the latched version and asynchronous version of this threshold are available on any of the
GPIOs. Automatic fast hopping based on RSSI is available. See “5.3.1.2. Automatic RX Hopping and Hop Table”.
5.3. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over the bands from 142–175,
283–350, 420–525, and 850–1050 MHz for the Si4460/61/63. The Si4464 offers frequency coverage in bands that
are not covered by Si4463/1/0. Using a  synthesizer has many advantages; it provides flexibility in choosing data
rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in
the digital domain through the fractional divider, which results in very precise accuracy and control over the
transmit deviation. The frequency resolution in the 850–1050 MHz band is 28.6 Hz with more resolution in the
other bands. The nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz
may be used. The modem configuration calculator in WDS will automatically account for the XTAL frequency being
used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed
by a configurable divider, which will divide the signal down to the desired output frequency band.
5.3.1. Synthesizer Frequency Control
The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will
automatically provide these settings, but the synthesizer equation is shown below for convenience. The APIs for
setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and
FREQ_CONTROL_FRAC0.
RF_channel
=


fc_inte
+
-^f-^c---_{2_}----^f₁-^r-₉-^a---^c--_
 ²-----^-_o----_uf--^r--_te--_d-^q---_i-^_v---^x---^o--Hz
Note: The fc_frac/2¹⁹ value in the above formula has to be a number between 1 and 2.
Table 13. Output Divider (Outdiv) Values for the Si4460/61/63
Outdiv
24
12
8
4
Lower (MHz)
142
284
420
850
Upper (MHz)
175
350
525
1050
Table 14. Output Divider (Outdiv) for the Si4464
Outdiv
24
16
12
8
6
4
Lower (MHz)
119
177
235
353
470
705
Upper (MHz)
159
239
319
479
639
960
32
Rev 1.2