SI4464 Datasheet, PDF (26/56 Pages) Silicon Laboratories – HIGH-PERFORMANCE

Si4464/63/61/60
4.2. Modulation Types
The Si446x supports five different modulation options: Gaussian frequency shift keying (GFSK), frequency-shift
keying (FSK), four-level GFSK (4GFSK), four-level FSK (4FSK), and on-off keying (OOK). Minimum shift keying
(MSK) can also be created by using GFSK settings. GFSK is the recommended modulation type as it provides the
best performance and cleanest modulation spectrum. The modulation type is set by the “MOD_TYPE[2:0]”
registers in the “MODEM_MOD_TYPE” API property. A continuous-wave (CW) carrier may also be selected for RF
evaluation purposes. The modulation source may also be selected to be a pseudo-random source for evaluation
purposes.
4.3. Hardware Configuration Options
There are different receive demodulator options to optimize the performance and mutually-exclusive options for
how the RX/TX data is transferred from the host MCU to the RF device.
4.3.1. Receive Demodulator Options
There are multiple demodulators integrated into the device to optimize the performance for different applications,
modulation formats, and packet structures. The calculator built into WDS will choose the optimal demodulator
based on the input criteria.
4.3.1.1. Synchronous Demodulator
The synchronous demodulator's internal frequency error estimator acquires the frequency error based on a
101010 preamble structure. The bit clock recovery circuit locks to the incoming data stream within four transactions
of a “10” or “01” bit stream. The synchronous demodulator gives optimal performance for 2- or 4-level FSK or
GFSK modulation that has a modulation index less than 2.
4.3.1.2. Asynchronous Demodulator
The asynchronous demodulator should be used OOK modulation and for FSK/GFSK/4GFSK under one or more of
the following conditions:
Modulation index > 2
Non-standard preamble (not 1010101... pattern)
When the modulation index exceeds 2, the asynchronous demodulator has better sensitivity compared to the
synchronous demodulator. An internal deglitch circuit provides a glitch-free data output and a data clock signal to
simplify the interface to the host. There is no requirement to perform deglitching in the host MCU. The
asynchronous demodulator will typically be utilized for legacy systems and will have many performance benefits
over devices used in legacy designs. Unlike the Si4432/31 solution for non-standard packet structures, there is no
requirement to perform deglitching on the data in the host MCU. Glitch-free data is output from Si446x devices, and
a sample clock for the asynchronous data can also be supplied to the host MCU; so, oversampling or bit clock
recovery is not required by the host MCU. There are multiple detector options in the asynchronous demodulator
block, which will be selected based upon the options entered into the WDS calculator. The asynchronous
demodulator's internal frequency error estimator is able to acquire the frequency error based on any preamble
structure.
4.3.2. RX/TX Data Interface With MCU
There are two different options for transferring the data from the RF device to the host MCU. FIFO mode uses the
SPI interface to transfer the data, while direct mode transfers the data in real time over GPIO.
4.3.2.1. FIFO Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is
accessed by writing Command 66h followed directly by the data/clk that the host wants to write into the TX FIFO.
The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data the host would
like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin.
In TX mode, if the packet handler is enabled, the data bytes stored in FIFO memory are “packaged” together with
other fields and bytes of information to construct the final transmit packet structure. These other potential fields
include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX
mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
properties. If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into
FIFO memory; no other fields (such as Preamble or Sync word) will be automatically added to the bytes stored in
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