HYB39S64400 Datasheet, PDF (8/53 Pages) Siemens Semiconductor Group – 64 MBit Synchronous DRAM

HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Row Activate (ACT)
Read (READ)
Read w/ Autoprecharge
(READA)
Write (WRITE)
Write w/ Autoprecharge
(WRITEA)
Device CKE CKE CS RAS CAS WE DQM A0-9, A10 BS0
State n-1 n
A11
BS1
Idle³ H
X
L
L
H
HX
V
V
V
Active³ H
X
L
H
L
HXV L V
Active³ H
X
L
H
L
HXVHV
Active³ H
X
L
H
L
LXVLV
Active³ H
X
L
H
L
L XVHV
Row Precharge (PRE)
Any H
X
L
L
H
LXXLV
Precharge All (PREA)
Any H
X
L
L
H
L XXHX
Mode Register Set (MRS)
Idle
H
X
L
L
L
LXVVV
No Operation (NOP)
Any H
X
L
H
H
HXXXX
Device Deselect (INHBT)
Any
H
X
H
X
X
XXXXX
Auto Refresh (REFA)
Idle
H
H
L
L
L
HXXXX
Self Refresh Entry (REFS-EN) Idle
H
L
L
L
L
HXXXX
Self Refresh Exit (REFS-EX) Idle
H
X
X
X
(Self L
H
L
H
H
X
X
X
X
X
Refr.)
Power Down Entry (PDN-EN) Idle
H
X
X
X
Active⁵ H
L
L
H
H
X
X
X
X
X
Power Down Exit (PDN-EX)
Any
H
X
X
X
(Power L
Down)
H
L
H
H
L
X
X
X
X
Data Write/Output Enable
Active H
X
X
X
X
XL
XXX
Data Write/Output Disable
Active H
X
X
X
X
XHXXX
Note:
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before
the commands are provided.
3. This is the state of the banks designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle
device is clock suspend mode.
Semiconductor Group
8