HYB39S64400 Datasheet, PDF (34/53 Pages) Siemens Semiconductor Group – 64 MBit Synchronous DRAM

12.2 Clock Suspension During Burst Read (Using CKE)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 _T11 T12 _{T13 T14 T15 T16 T17 T18 T19 T20 T21 T22}
CLK
t_CK3
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr
RAx
DQM
DQ ^Hi-Z
Activate
Command
Bank A
CAx
Read
Command
Bank A
t_CSL
t_CSL
t_CSL
Ax0
Ax1
Ax2
t_HZ
Ax3
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
Clock Suspend
3 Cycles