HYB39S64400 Datasheet, PDF (52/53 Pages) Siemens Semiconductor Group – 64 MBit Synchronous DRAM

22.1 Precharge Termination of a Burst
Burst Length = 8 or Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 _T11 T12 _{T13 T14 T15 T16 T17 T18 T19 T20 T21 T22}
CLK
t_CK2
CKE ^High
CS
RAS
CAS
WE
BS
AP
RAx
RAy
RAz
Addr
RAx
CAx
DQM
RAy
CAy
t_RP
DQ ^Hi-Z
DAx0 DAx1 DAx2 DAx3
Activate
Command
Bank A
Write
Precharge
Command
Bank A
Command
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
Activate
Command
Bank A
Read
Command
Bank A
RAz
CAz
t_RP
t_RP
Ay0 Ay1 Ay2
Az0 Az1 Az2
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.