HYB39S64400 Datasheet, PDF (18/53 Pages) Siemens Semiconductor Group – 64 MBit Synchronous DRAM

HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have V_il = 0.4 V and V_ih = 2.4 V with the timing referenced to the 1.5 V
crossover point. The transition time is measured between V_ih and V_il. All AC measurements assume t_T=1ns
with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 50 pF only,
without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V..
CLOCK
tCL
tSETUP tHOLD
tCH
2.4 V
0.4 V
t_T
+ 1.5 V
50 Ohm
Z=50 Ohm
I/O
INPUT
1.5V
50 pF
OUTPUT
tAC
tLZ
tAC
tOH
1.5V
I/O
50 pF
Measurement conditions for
tac and toh
fig.1
tHZ
3. If clock rising time is longer than 1 ns, a time (t_T/2 - 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (t_T -1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
Semiconductor Group
18