HYB39S64400 Datasheet, PDF (50/53 Pages) Siemens Semiconductor Group – 64 MBit Synchronous DRAM

21.1 Full Page Write Cycle
Burst Length = Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T
T
T
T
T
TT
T
T
T
T
T
T
T
T
T
T
CLK
t_CK2
CKE ^High
CS
RAS
CAS
WE
BS
AP
RAx
RBx
RBy
Addr
RAx
CAx
RBx
CBx
RBy
DQM
DQ ^Hi-Z
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
Activate
Command
Bank A
Write
Command
Bank A
Activate
Write
Command
Command
Data is ignored. Precharge
Bank B
Bank B
Command
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Bank B
Burst Stop
Command
Activate
Command
Bank B