HYB39S64400 Datasheet, PDF (49/53 Pages) Siemens Semiconductor Group – 64 MBit Synchronous DRAM

20.2 Full Page Read Cycle
Burst Length = Full Page, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T
T
TT
T
T
T
T
T
T
T
T
T
T
CLK
t_CK3
CKE ^High
CS
RAS
CAS
WE
BS
AP
RAx
RBx
RBy
Addr
RAx
DQM
Hi-Z
DQ
Activate
Command
Bank A
CAx
RBx
CBx
RBy
t_RRD
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
The burst counter wraps
Full Page burst operation does not
terminate when the length is
satisfied; the burst counter
increments and continues
bursting beginning with
Precharge
Command
Bank B
from the highest order the starting address.
page address back to zero
Burst Stop
during this time interval.
Command
Activate
Command
Bank B