HYB39S64400 Datasheet, PDF (45/53 Pages) Siemens Semiconductor Group – 64 MBit Synchronous DRAM

18.2 Random Row Read (Interleaving Banks) with Precharge
Burst Length = 8, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 _T11 T12 _{T13 T14 T15 T16 T17 T18 T19 T20 T21 T22}
CLK
t_CK3
CKE ^High
CS
RAS
CAS
WE
BS
AP
RBx
RAx
RBy
Addr
DQM
RBx
CBx
t_RCD
Hi-Z
DQ
Activate
Command
Bank B
Read
Command
Bank B
RAx
CAx
t_AC3
RBy
CBy
t_RP
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A