HYB39S164400 Datasheet, PDF (5/64 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
CKE CKE Buffer
CLK CLK Buffer
Self
Refresh Clock
Row
Address
Counter
A0
A1
A2
A3
12
A4
A5
A6
A7
A8
12
A9
A10
A11 (BS)
CS
CS Buffer
RAS
RAS Buffer
CAS
CAS Buffer
2048
2048 x 1024
Memory Bank A
Bank A
Row/Column
Select
Sense Amplifiers
Column Decoder and DQ Gate
11 ^{Predecode A}
3
Sequential
Control
Bank A
8
Data Latches
8
11 ^{Mode Register}
8
Sequential
Control
3 _{Bank B}
11 Predecode B
Data Latches
8
Bank B
Row/Column
Select
Column Decoder and DQ Gate
Sense Amplifiers
4
DQ0
DQ1
DQ2
DQ3
WE
WE Buffer
DQM ^{DQM Buffer}
2048
2048
Memory Bank B
2048 x 1024
Block Diagram for HYB39S16400BT (2 banks x 4M x 4 SDRAM)
Semiconductor Group
5