HYB39S164400 Datasheet, PDF (25/64 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND ^NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 1
t_CK1, DQs’
CAS latency = 2
t_CK2, DQs’
CAS latency = 3
t_CK3, DQs’
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
dont’ care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
dont’ care
dont’ care
Input data for the Write is ignored.
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data must be removed from the DQs’ at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
7.1 Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
BANK A
ACTIVE
NOP
CAS latency = 1
DQs’
CAS latency = 2
DQs’
CAS latency = 3
DQs’
NOP
WRITE A
Auto-Precharge
DIN A0
DIN A0
DIN A0
NOP
NOP
NOP
NOP
t_DPL
t_RP
* ^{DIN A1}
t_DPL
t_RP
DIN A1
*
t_DPL
t_RP
DIN A1
*
* ^{Begin Autoprecharge}
Bank can be reactivated after trp
NOP
Semiconductor Group
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