HYB39S164400 Datasheet, PDF (19/64 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Read & Write with Auto-Precharge
7.1 Burst Write with Auto Precharge
7.2 Burst Read with Auto Precharge
8. Burst Termination
8.1 Termination of a Burst Read Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Clock Suspension (using CKE)
12.1 Clock Suspension During Burst ReadCAS Latency = 1
12. 2 Clock Suspension During Burst ReadCAS Latency = 2
12. 3 Clock Suspension During Burst ReadCAS Latency = 3
12. 4 Clock Suspension During Burst WriteCAS Latency = 1
12. 5 Clock Suspension During Burst WriteCAS Latency = 2
12. 6 Clock Suspension During Burst WriteCAS Latency = 3
13. Power Down Mode and Clock Suspend
14. Auto Refresh (CBR)
15. Self Refresh ( Entry and Exit)
16. Random Column Read ( Page within same Bank)
16.1 CAS Latency = 1
16.2 CAS Latency = 2
16.3 CAS Latency = 3
17. Random Column Write ( Page within same Bank)
17.1 CAS Latency = 1
17.2 CAS Latency = 2
17.3 CAS Latency = 3
Semiconductor Group
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