HYB39S164400 Datasheet, PDF (20/64 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

Timing Diagrams (contd’ )
18. Random Row Read ( Interleaving Banks)
18.1 CAS Latency = 1
18.2 CAS Latency = 2
18.3 CAS Latency = 3
19. Random Row Write ( Interleaving Banks)
19.1 CAS Latency = 1
19.2 CAS Latency = 2
19.3 CAS Latency = 3
20. Full Page Read Cycle (optional feature)
20.1 CAS Latency = 1
20.2 CAS Latency = 2
20.3 CAS Latency = 3
21. Full Page Write Cycle (optional feature)
21.1 CAS Latency = 1
21.2 CAS Latency = 2
21.3 CAS Latency = 3
22. Precharge Termination of a Burst
22.1 CAS Latency = 1
22.2 CAS Latency = 2
22.3 CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
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