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LC89058W-E Datasheet, PDF (6/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver
LC89058W-E
7 Common and Different Points between LC89057W-VF4A-E and LC89058W-E
7.1 Common Features
Table 7.1: Common of LC89057W-VF4A-E and LC89058W-E functions (Hardware/Software Compatibility)
Item
LC89057W-VF4A-E
LC89058W-E
Package
Supply voltage
DIR reception range
Oscillation amplifier input frequency
2-system-clock pin output
S/PDIF inputs
Serial data input
Non-PCM flag output
Emphasis information output
DTS-CD/LD detection function
General-purpose I/O
Chip address setting
Mode setting external resistor
Microcontroller interface
Register configuration
SQFP48(9x9)
3.3V single source
32kHz to 192kHz
12.288MHz/24.576MHz
RMCK, RBCK, RLRCK, SBCK, SLRCK
7 maximum (1 coaxial, 6 optical)
SDIN
AUDIO
EMPHA (consumer and professional)
14-bit format detection supported
4 bits
4 addresses maximum (master/salve supported)
4 resistors used
CCB (SANYO-proprietary IF)
4 command address bits, 8 data bits
←
←
←
←
← SBCK: 16fs, SLRCK: 1/4 output added
←
←
←
← MOUT (consumer only)
←
←
←
←
← DI input regulations has.
←
7.2 Removed Functions
Table 7.2: Differences between LC89057W-VF4A-E and LC89058W-E (Removed Functions)
Item
LC89057W-VF4A-E
LC89058W-E
Function
S/PDIF unlock path switching
External clock synchronization mode
R and S system clock synchronization
Data output format
C, V, U pin output
Input fs computed output
Microcontroller interrupt signal
Modulation and demodulation
Yes
Yes
Asynchronous system
16, 20, 24 bits/left-justified/right-justified MSB, I2S
Yes
16kHz to 192kHz
Yes (Low pulse, Low level output)
Modulation removed (demodulation only)
Removed
Removed
Synchronization clock (SELMTD, RCKSEL removed)
Right-justified removed (left-justified MSB, I2S only)
Removed
32kHz to 192kHz (fs < 32kHz, removed)
Pulse output mode removed (level output only)
7.3 Added or Modified Functions
Table 7.3: Differences between LC89057W-VF4A-E and LC89058W-E (Added or Modified Functions)
Item
LC89057W-VF4A-E
LC89058W-E
Oscillation amplifier initial setting
Suspended while PLL is locked
Permanent operation
PLL clock output
256fs or 512fs
512fs
Master clock output
Multiple of input fs is output
Multiple of input fs on each band is output
Clock output when XIN source
No limitation
RBCK and SBCK must 1/2 or less of RMCK
Clock switching
Clock count is preserved (to maintain continuity)
Switched during the CKST pulse output
RMCK and CKST polarity
Polarity cannot be switched
Polarity can be switched
S/PDIF reception limitation
Reflected only to error flag.
Reflected to both error flag and clock output
S/PDIF input detection range
32kHz to 96kHz (XIN=24.57M/12.28MHz)
32kHz to 192kHz (XIN=24.576MHz only)
Input fs value monitor output
Microcontroller interface output only
Microcontroller interface and pin outputs
General-purpose I/O input pin
No timing control
Polling supported (with interrupt)
General-purpose I/O input/output pin
Parallel I/O function only
Internal selector input also supported.
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No.A1056-6/64