LC89058W-E Datasheet, PDF (50/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
CCB address: 0xE8, Command address: 9; RERR output setting
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
1
0
0
1
0
0
CAU
CAL
DI15
ERWT1
DI14
ERWT0
DI13
FSERR
DI12
RESTA
DI11
0
DI10
0
DI9
REDER
DI8
RESEL
RESEL
RERR output contents setting
0: PLL lock error or data error (initial value)
1: PLL lock error or data error or non-PCM data
REDER
Setting of parity error flag output within 8 times in a row
0: Output only when non-PCM data is recognized (initial value)
1: Output only during sub-frame for which error was generated
RESTA
RERR output condition setting
0: Output PLL status all the time (Output PLL status even during XIN source)
(initial status)
1: Forcibly output error (Set "H" to RERR forcibly)
FSERR
Setting of error flag output condition according to fs change
0: Reflect fs changes to error flag (initial value)
1: Don't reflect fs changes to error flag
ERWT [1:0]
Setting of RERR wait time after PLL is locked
00: Cancel error after preamble B is counted 3 (initial value)
01: Cancel error after preamble B is counted 24
10: Cancel error after preamble B is counted 12
11: Cancel error after preamble B is counted 6
_________
• Non-PCM data is identical to the detection data output to AUDIO.
• Output data is muted if an error occurs due to non-PCM data with RESEL.
• The RESTA setting is not reflected to the output pins of data and clock.
• For FSERR, the fs calculation result obtained while the oscillation amplifier is stopped is not reflected. In this case, fs
changes consist of only channel status fs information.
• ERWT[1:0] defines the interval of time for RERR to output error cancellation ("L") after PLL is locked. Since
demodulated audio data is output after RERR cancels an error, you need to change this setting if the situation that the
head of data is missing is a problem.
No.A1056-50/64