LC89058W-E Datasheet, PDF (52/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

DI7
1
DI15
0
PLLACC
PLLDV0
PLLDV1
RMCKP
CKSTP
LC89058W-E
CCB address: 0xE8; Command address: 11; System settings 3
DI6
DI5
DI4
DI3
DI2
DI1
DI0
1
0
0
0
0
CAU
CAL
DI14
0
DI13
CKSTP
DI12
RMCKP
DI11
0
DI10
PLLDV1
DI9
PLLDV0
DI8
PLLACC
PLL clock lock frequency setting
0: Manual setting (initial value)
1: Automatic control (see 10.1.6.)
Set the PLL clock generated when 32kHz, 44.1kHz or 48kHz is received with PLLACC=1
0: 512fs output (initial value)
1: 256fs output
Set the PLL clock generated when 88.2kHz or 96kHz is received with PLLAC=1
0: 256fs output (initial value)
1: 512fs output
DIR block RMCK output setting
0: Normal output (initial value)
1: Inverted output
CKST output polarity setting
0: Normal high output (initial value)
1: Normal low output
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