LC89058W-E Datasheet, PDF (45/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
CCB address: 0xE8; Command address: 4; S system output clock setting
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
0
1
0
0
0
0
CAU
CAL
DI15
XSLRCK1
DI14
XSLRCK0
DI13
XSBCK1
DI12
XSBCK0
DI11
PSLRCK1
DI10
PSLRCK0
DI9
PSBCK1
DI8
PSBCK0
PSBCK [1:0]
Setting of SBCK frequency while PLL is locked
00: 64fs output (initial value)
01: 128fs output
10: 32fs output
11: 16fs output
PSLRCK [1:0]
Setting of SLRCK frequency while PLL is locked
00: fs output (initial value)
01: 2fs output
10: fs/2 output
11: fs/4 output
XSBCK [1:0]
Setting of SBCK frequency during XIN source
00: 3.072MHz output (RMCK≥6.144MHz) (initial value)
01: 6.144MHz output (RMCK≥12.288MHz)
10: 12.288MHz output (RMCK=24.576MHz)
11: Muted
XSLRCK [1:0]
SLRCK output frequency setting during XIN source
00: 48kHz output (initial value)
01: 96kHz output
10: 192kHz output
11: Muted
• Setting of XSBCK [1:0] relate to setting of RMCK output clock. SBCK output clock is set to become 1/2 or less of
RMCK output clock at XIN source.
No.A1056-45/64