LC89058W-E Datasheet, PDF (26/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
10.1.10 Output clocks generated when input S/PDIF reception is limited
• _{The same processing performed when the PLL is unlocked is carried out if an S/PDIF input exceeding the reception}
range limit (which can be defined by FSLIM[1:0]) is supplied. The clock source is then switched to the XIN clock and
clocks are output from respective clock pins.
DIN0-6
PLL status
RERR
RMCK
RBCK
RLRCK
DIN0-6
PLL status
RERR
RMCK
RBCK
RLRCK
fs=44.1kHz
LOCK
fs=192kHz
LOCK
fs=96kHz
LOCK
PLL clock
PLL clock
(a) When set to FSLIM[1:0]=00 (No limit on inputs)
XIN clock
fs=44.1kHz
LOCK
fs=192kHz
LOCK
PLL clock
UNLOCK
fs=96kHz
LOCK
PLL clock
XIN clock
PLL clock
(b) When set to FSLIM[1:0]=01 (Receive frequency is limited to 96kHz or lower)
DIN0-6
PLL status
RERR
RMCK
RBCK
RLRCK
fs=44.1kHz
LOCK
fs=192kHz
LOCK
fs=96kHz
LOCK
PLL clock
XIN clock
(c) When set to FSLIM[1:0]=10 (Receive frequency is limited to 48kHz or lower)
Figure 10.6 Output Clocks Generated When Input Data Reception Is Limited
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