LC89058W-E Datasheet, PDF (44/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
CCB address: 0xE8; Command address: 3; R system output clock setting
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
0
0
1
1
0
0
CAU
CAL
DI15
XRLRCK1
DI14
XRLRCK0
DI13
XRBCK1
DI12
XRBCK0
DI11
XRSEL1
DI10
XRSEL0
DI9
PRSEL1
DI8
PRSEL0
PRSEL [1:0]
Setting of RMCK output frequency while PLL is locked
(enabled when PLLACC is set to “0”)
00: 512fs×1/2 (256fs) (initial value)
01: 512fs×1/1 (512fs)
10: 512fs×1/4 (128fs)
11: Muted
XRSEL [1:0]
Setting of RMCK output frequency during XIN source
00: 1/1 of XIN input frequency (initial value)
01: 1/2 of XIN input frequency
10: 1/4 of XIN input frequency
11: Muted
XRBCK [1:0]
Setting of RBCK output frequency during XIN source
00: 3.072MHz output (RMCK≥6.144MHz) (initial value)
01: 6.144MHz output (RMCK≥12.288MHz)
10: 12.288MHz output (RMCK=24.576MHz)
11: Muted
XRLRCK [1:0]
Setting of RLRCK output frequency during XIN source
00: 48kHz output (initial value)
01: 96kHz output
10: 192kHz output
11: Muted
• Don’t do the setting to which RMCK=3.072MHz is output by XRSEL [1:0]=10(1/4 output) setting when
XIN=12.288MHz is input because it doesn't satisfy the output setting condition of RBCK and SBCK.
• Setting of XRBCK [1:0] relate to setting of RMCK output clock. RBCK output clock is set to become 1/2 or less of
RMCK output clock at XIN source.
No.A1056-44/64