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LC89058W-E Datasheet, PDF (24/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver | |||
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LC89058W-E
10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK)
⢠The relationships between the output clock and switch function are shown below.
⢠PLL in the figure indicates the PLL source and XIN the XIN source.
⢠The contents in the quotation marks âââââ by the switch function blocks correspond to the write command names.
⢠The broken lines connecting the switches indicate coordinated switching.
⢠Lock/Unlock is switched automatically by PLL locking/unlocking.
Master
Clock
Generator
PLL Source
512fs
Xâtal Source
12.288MHz
24.576MHz
512fs
âPLLDV0â
âPLLDV1â
1/1
1/2
1/4
Input fs
Auto
âPRSEL[1:0]â
512fs
256fs
128fs
Mute
âXINSELâ
12.288MHz
24.576MHz
Lock / Unlock
âOCKSELâ
âPLLACCâ
PLL
âEXTSELâ
âXRSEL[1:0]â
1/1
1/2
1/4
Mute
XIN
GPIO0
âXMSEL[1:0]â
1/1
1/2
Mute
64fs
PLL
âRMCKPâ
âEMCKPâ
RMCK
XMCK
âXRBCK[1:0]â
12.288MH
6.144MHz
3.072MHz
Mute
XIN
GPIO1
fs
PLL
RBCK
âPSBCK[1:0]â
128fs
64fs
32fs
16fs
âPSLRCK[1:0]â
2fs
fs
fs/2
fs/4
âXRLRCK[1:0]â
192kHz
96kHz
48kHz
Mute
XIN
GPIO2
âSBCKPâ
PLL
âXSBCK[1:0]â
12.288MH
6.144MHz
3.072MHz
Mute
XIN
âSLRCKPâ
PLL
âXSLRCK[1:0]â
192kHz
96kHz
48kHz
Mute
XIN
RLRCK
Master / Slave
SBCK
SLRCK
Figure 10.4 Clock Output Block Diagram
No.A1056-24/64
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