LC89058W-E Datasheet, PDF (46/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
CCB address: 0xE8; Command address: 5; Clock source switching; RDATA output setting
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
0
1
0
1
0
0
CAU
CAL
DI15
0
DI14
RDTMUT
DI13
RDTSTA
DI12
RDTSEL
DI11
0
DI10
DI9
DI8
0
OCKSEL
0
OCKSEL
Clock source setting
0: Use XIN clock as source while PLL is unlocked (initial value)
1: Use XIN clock as source regardless of PLL status
RDTSEL
RDATA output setting while PLL is unlocked
0: Output SDIN data while PLL is unlocked (initial value)
1: Mute while PLL is unlocked
RDTSTA
RDATA output setting
0: According to RDTSEL (initial value)
1: Output SDIN input data regardless of PLL status
RDTMUT
RDATA mute setting
0: Output data selected with RDTSEL (initial value)
1: Muted
• When the oscillation amplifier is set to the permanent continuous operation mode with AMPOPR [1:0] or fs changes
are set not to be reflected to the error flag with FSERR, OCKSEL can switch the clock source while maintaining the
RERR status.
• The phase of R system clock and S system clock synchronize.
• To input data to SDIN, select a clock synchronized with the SDIN input data.
• The XIN source can be switched while maintaining the PLL locked status. However, since switching between clock
and data output can be set independently; it is recommended to select mute or SDIN data for the output data when
XIN source is switched.
• If the oscillation amplifier is set to stop automatically when the PLL gets locked, XIN source switching from the PLL
locked status disables the clock output. Be sure to set the oscillation amplifier to the continuous operation mode when
switching the clock source to the XIN source.
No.A1056-46/64