LC89058W-E Datasheet, PDF (54/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
CCB address: 0xE8; Command address: 13; PLL clock
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
1
1
1
0
0
0
CAU
CAL
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
FSSEL1
FSSEL0
0
0
PTOXW1
PTOXW0
0
0
PTOXW[1:0]
Setting of clock switch wait time
00: Clock switching after 2.67ms from when the PLL lock status is identified (initial value)
01: Clock switching after 1.33ms from when the PLL lock status is identified
10: Clock switching after 0.67ms from when the PLL lock status is identified
11: Clock switching after when the PLL lock status is identified
FSSEL[1:0]
MOUT output contents setting (output “L” when PLL unlock status or when a value other than
those listed below is calculated)
00: Output “H” when 32kHz/44.1kHz/48kHz is calculated (Initial value)
01: Output “H” when 64kHz/88.2kHz/96kHz is calculated
10: Output “H” when 128kHz/176.4kHz/192kHz is calculated
11: Output “H”when 64kHz/88.2kHz/96kHz or higher is calculated
No.A1056-54/64