LC89058W-E Datasheet, PDF (42/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

12.2.2 Details of write commands
LC89058W-E
CCB address: 0xE8; Command address: 0; System setting 1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
0
0
0
0
0
0
CAU
DI15
TESTM
DI14
0
DI13
0
DI12
0
DI11
0
DI10
0
DI9
DOEN
SYSRST
System reset
0: Don't reset (initial value)
1: Reset circuits other than command registers
DOEN
DO pin output setting
0: Output (initial value)
1: Always high impedance state (read disabled)
TESTM
Test mode setting
0: Normal operation (initial value)
1: Enter test mode
• When reset by SYSRST is performed, RBCK outputs “L” and BLRCK outputs “H.”
DI0
CAL
DI8
SYSRST
CCB address: 0xE8; Command address: 1; System setting 2
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
0
0
0
1
0
0
CAU
CAL
DI15
0
DI14
DI13
DI12
DI11
DI10
DI9
DI8
0
FSLIM1
FSLIM0
RXMON
AOSEL
0
MOSEL
MOSEL
AOSEL
RXMON
FSLIM[1:0]
MOUT output contents setting
0: Output channel status emphasis information (initial value)
1: Output input data fs calculation results (output conditions are given by FSSEL[1:0].)
AUDIO output mode
0: Only output channel status bit 1 (initial value)
1: Output channel status bit 1, IEC61937 or DTS-CD/LD detection flag
Setting digital audio data (S/PDIF) input status monitoring
0: Don’t monitor S/PDIF input status (initial value).
1: Monitor S/PDIF input status
Setting of sampling frequency reception range for input digital signal
00: No limit (initial value)
01: fs≤96kHz (when exceeded, data is muted and clock is set to XIN system output)
10: fs≤48kHz (when exceeded, data is muted and clock is set to XIN system output)
11: Reserved
No.A1056-42/64