K4B2G1646C-HCF8000 Datasheet, PDF (49/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
[ Table 50 ] Timing Parameters by Speed Bins for DDR3-1600 to DDR3-2133 (Cont.)
Speed
Parameter
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Pre-
charge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands re-
quiring a locked DLL
Symbol
tXP
tXPDLL
CKE minimum pulse width
tCKE
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tCPDED
tPD
tACTPDEN
tPRPDEN
tRDPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
Timing of WR command to Power Down entry
(BL4MRS)
tWRPDEN
Timing of WRA command to Power Down entry
(BL4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
ODT high time without write command or with write command
and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with DLL fro-
zen)
Asynchronous RTT turn-off delay (Power-Down with DLL fro-
zen)
RTT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff reference
RTT dynamic change skew
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode is pro-
grammed
DQS/DQS delay after tDQS margining mode is programmed
Write leveling setup time from rising CK, CK crossing to rising
DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing to rising
CK, CK crossing
Write leveling output delay
Write leveling output error
tWRAPDEN
tREFPDEN
tMRSPDEN
ODTH4
ODTH8
tAONPD
tAOFPD
tAON
tAOF
tADC
tWLMRD
tWLDQSEN
tWLS
tWLH
tWLO
tWLOE
DDR3-1600
MIN
MAX
max
(3nCK,6ns)
max
(10nCK,
24ns)
max
(3nCK,5ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4 +WR
+1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
2
8.5
2
8.5
-225
225
0.3
0.7
0.3
0.7
40
-
25
-
165
-
165
-
0
7.5
0
2
DDR3-1866
MIN
MAX
max(3nCK,6ns
)
-
max(10nCK,24
ns)
-
max(3nCK,5ns
)
2
tCKE(min)
1
1
RL + 4 +1
-
-
9*tREFI
-
-
-
WL + 4 +(tWR/
tCK(avg))
-
WL + 4 +WR
+1
-
WL + 2 +(tWR/
tCK(avg))
-
WL +2 +WR +1
-
1
-
tMOD(min)
-
4
-
6
-
2
8.5
2
8.5
-195
195
0.3
0.7
0.3
0.7
40
-
25
-
140
-
140
-
0
7.5
0
2
DDR3-2133
MIN
MAX
max(3nCK,6n
s)
-
max(10nCK,2
4ns)
-
max(3nCK,5n
s)
2
tCKE(min)
2
2
RL + 4 +1
-
-
9*tREFI
-
-
-
WL + 4 +(tWR/
tCK(avg))
-
WL + 4 +WR
+1
-
WL + 2 +(tWR/
tCK(avg))
-
WL +2 +WR
+1
-
2
-
tMOD(min)
-
4
-
6
-
2
8.5
2
8.5
-180
180
0.3
0.7
0.3
0.7
40
-
25
-
125
-
125
-
0
7.5
0
2
Units
nCK
tCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ps
tCK(avg)
tCK(avg)
tCK
tCK
ps
ps
ns
ns
NOTE
2
15
20
20
9
10
9
10
20,21
7,f
8,f
f
3
3
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